1. Field of the Invention
The present invention relates to a time constant automatic adjustment circuit and, more particularly, to a time constant automatic adjustment circuit for a filter circuit incorporated into an IC.
2. Description of the Prior Art.
In general, a filter circuit employs a time constant circuit for determining the frequency characteristics of the circuit. The time constant circuit requires that the time constant of the circuit be maintained stably at a predetermined value. A time constant circuit is usually constituted by resistive elements and capacitive elements. When such a filter circuit is fabricated as an integrated circuit (referred as IC hereafter), it is necessary to adjust the time constant of the time constant circuit externally, since the resistances or the capacitances of the resistive elements and capacitive elements are not precise. Further, the resistances or the capacitances of the resistive elements and capacitive elements are unstable in relation to temperature change and long term use.
Referring now to FIGS. 1 to 4, some conventional adjustments for some typical filter circuits or time constant circuits will be explained. FIGS. 1 to 4 show four typical examples of a filter circuit, e.g., a low-pass filter.
First, the filter circuit shown in FIG. 1 has a time constant circuit comprised of a resistor 10 and a variable capacitor 12. The resistor 10 is connected between an input terminal 14 for receiving input signal Vin and an output terminal 16 for supplying output signal Vout. The variable capacitor 12 is connected between the output terminal 16 and a control terminal 18 for receiving a control signal Vc for adjustment. According to the connection of the resistor 10 and the variable capacitor 12, the time constant circuit forms a low-pass filter or an integrating circuit. The capacitance of the variable capacitor 12 varies in response to changes in the value of the control signal Vc on the control terminal 18.
The filter circuit shown in FIG. 2 has a time constant circuit comprised of a field effect transistor (referred as FET hereafter) 20 and a capacitor 22. The FET 20 is connected between an input terminal 14 for receiving an input signal Vin and an output terminal 16 for supplying output signal Vout. The capacitor 22 is connected between the output terminal 16 and a reference potential terminal, e.g., the grounded terminal 24. The FET 20 has a gate connected to a control terminal 18 for receiving a control signal Vc for adjustment. The impedance of the FET 20 varies in response to changes of the value of the control signal Vc on the control terminal Vc.
The filter circuit shown in FIG. 3 has a time constant circuit comprised of a bipolar transistor 26, a variable current source 28 and a capacitor 22. The base and the emitter of the bipolar transistor 26 are connected to an input terminal 14 for receiving an input signal Vin and an output terminal 16 for supplying output signal Vout, respectively. The collector of the bipolar transistor 26 is connected to a power source terminal 30 for receiving a power source voltage Vcc. The variable current source 28 is connected between the emitter of the bipolar transistor 26 and a reference potential terminal, e.g., the grounded terminal 24. The capacitor 22 is connected between the emitter of the bipolar transistor 26 and the grounded terminal 24, i.e., in parallel with the variable current source 28. The variable current source 28 is designed to receive a control signal Vc for adjustment on a control terminal 18. Thus, the current I28 of the variable current source 28 varies in response to the control signal Vc. The variable current source 28 supplies the bipolar transistor 26 with the variable current I28 in response to the control signal Vc, so that the equivalent emitter resistance of the bipolar transistor 26 is varied. The filter circuits, as shown in FIGS. 1 to 3, have a transfer characteristic G(LPF) as follows: EQU G(LPF)=1/(1+j.multidot.w.multidot.R.multidot.C) (1)
wherein j is the unit imaginary number (.sqroot.-1), w is the angle frequency of the input signal Vin, R is the resistance or impedance of the resistor 10, the FET 20 or the bipolar transistor 26 and C is the capacitance of the variable capacitor 12 or the capacitors 22. The transfer characterisic G(LPF) is influenced by variations in the amplitude of the input signal Vin. That is, when the amplitude of the input signal Vin varies, the variable capacitor 12 (FIG. 1), the FET 20 (FIG. 2), and the bipolar transistor 26 (FIG. 3) are affected directly by the variation of the input signal Vin. Thus, a distorsion is caused in the output signal Vout. As a result, it is difficult for the filter circuits to exhibit their full performance.
The fourth filter circuit, as shown in FIG. 4, has been devised for reducing the distortion in the output signal Vout. The filter circuit shown in FIG. 4 has a time constant circuit comprised of a first differential amplifier circuit 32 and a capacitor 22. The first differential amplifier circuit 32 and the capacitor 22 are connected to each other through a current conversion circuit 34.
In the first differential amplifier circuit 32, a pair of transistors 36, 38 are connected at their collectors to a power source terminal 30 through a current conversion circuit 34 for receiving a power source voltage Vcc, and at their emitters to a grounded terminal 24 through a current source 40. The current source 40 supplies the first differential amplifier circuit 32 with a current I40. Resistors 42, 44 are connected between the current source 40 and the emitters of the transistors 36, 38, respectively. The base of the transistor 36 is connected to an input terminal 14 for receiving an input signal Vin, while the base of the transistor 38 is connected to an output terminal 16 for supplying output signal Vout through a voltage divider 46. The voltage divider 46 multiplies the output voltage Vout to m times (m is a decimal number, i.e., m&lt;1). In other words, the voltage divider 46 divides the output voltage Vout by 1/m. The divided voltage is applied to the base of the transistor 38 of the first differential amplifier 32. The divided voltage of m Vout is fed back from the output terminal 16 to the first differential amplifier 32 through the voltage divider 46. The current conversion circuit 34 is comprised of transistors 48, 50 . . . 58, a reference voltage source 60 with a reference voltage Vref1 and a variable current source 28.
The transistors 48, 50 are connected between the power source terminal 30 and the collectors of the transistors 36, 38 of the first differential amplifier circuit 32, respectively. Their bases are commonly connected to the reference voltage source 60.
The transistors 52, 54 are connected at their collectors to the power source terminal 30 through the current mirror configuration active load circuit 64 and at their emitters to the grounded terminal 24 through the variable current source 28. The transistors 52, 54 thus constitute a second differential amplifier circuit 62. Their bases are connected to the collectors of the transistors 36, 38, respectively. The variable current source 28 is designed to receive a control signal Vc for adjustment on a control terminal 18. Thus, the current I28 of the variable current source 28 varies in response to the control signal Vc.
The transistors 56, 58 are connected between the power source terminal 30 and the collectors of the transistors 52, 54 of the second differential amplifier circuit 62, respectively. Their bases are commonly connected to the collector of the transistor 58. Accordingly, the transistors 56, 58 form a current mirror configuration active load circuit 64 for the second differential amplifier circuit 62. The collector of the transistor 56 is coupled to the output terminal 16 through a buffer amplifier 66. The capacitor 22 is connected between the collector of the transistor 52 and the grounded terminal 24.
The operation of the fourth filter circuit, as shown in FIG. 4, will be described.
When the input signal Vin on the input terminal 14 is applied to the base of the transistor 36 of the first differential amplifier circuit 32, collector currents I36 and I38 flow through the transistors 36, 38, respectively. The currents I36 and I38 also flow through the transistors 48, 50, respectively. Collector currents I52 and I54 flow through the transistors 52 and 54 of the second differential amplifier circuit 62 in the current conversion circuit 34, respectively. Since the bases of the transistors 48, 50 are connected with each other, the currents I36 and I38 have a relation defined by a logarithmic (Ln) characteristic of PN junctions in the transistors 48 and 50. Since the emitters of the transistors 52, 54 are connected with each other, the currents I52 and I54 have a relation defined by an exponential (Exp) characteristic of PN junctions in the transistors 52 and 54. As is well known, the logarithmic (Ln) characteristic and the exponential (Exp) characteristic compensate for each other. Thus, the following relation is maintained between the collector currents I36, I38, I52 and I54: EQU I36/I38=I54/I52 (2)
Thereupon, the collector currents I36, I38, I52 and I54 are able to be expressed as follows: EQU I36=I40/2+.DELTA.i32 EQU I38=I40/2-.DELTA.i32 EQU I52=I28/2+.DELTA.i62 EQU I54=I28/2-.DELTA.i62
wherein .DELTA.i32 is a variable component of a current flowing through the first differential amplifier 32, and .DELTA.i62 is a variable component of a current flowing through the second differential amplifier 62. From the above equations, the following equation for the variable component .DELTA.i62 is obtained: EQU i62=(I28/I40).multidot..DELTA.i32
The variable current component .DELTA.i62 flows into the capacitor 22 from both transistors 56, 58 of the second differential amplifier 62. The variable current component i62 from the transistor 56 directly flows into the capacitor 22. The variable current component .DELTA.i62 from the transistor 58 flows into the capacitor 22 via the current mirror configuration load circuit 64. Therefore, two times the variable current component .DELTA.i62, i.e., a current of 2.multidot..DELTA.i62, is fed into the capacitor 22. Thus, the output signal Vout on the output terminal 16 becomes as follows: ##EQU1## wherein C22 is the capacitance of the capacitor 22.
When this output signal Vout is negatively fed back to the first differential amplifier 32 through the voltage divider 46, the variable current component .DELTA.i32 of the first differential amplifier 32 is given as follows; EQU i32=(Vin-m.multidot.Vout)/ (R42+R44) (4)
wherein R42, R44 are resistances of the resistors 42, 44, respectively.
From the equations (3) and (4), the following equation is obtained: EQU Vout/Vin=1/[m+j.multidot.w.multidot.C22.multidot.(R42+R44).multidot.I40/(2. multidot.I28)] (5)
As is made clear from a comparison between the equations (1) and (5), these filter circuits shown in FIGS. 1 through 4 have the same frequency characteristic.
The time constant of the fourth filter circuit, as shown in FIG. 4, can be arbitrarily set if the conversion ratio of the current conversion circuit 34 is adjusted through the control of the current I28 of the variable current source 28. The conversion ratio of the current conversion circuit 34 can be adjusted through the control of the current I40 of the variable current source 40, instead of the control of the current I28 of the variable current source 28. That is, the current source of the first differential amplifier 32 is made variable and the current source of the second differential amplifier 62 is made constant.
In the fourth filter circuit, the variablity of the time constant responds to the variable current source 28 (or the current source 40), but not to the resistors 42, 44 or the capacitor 22. As a result, the variablity of the time constant does not respond to amplitude changes of the input signal Vin.
In the conventional filter circuits, as shown in FIGS. 1 to 4, the time constant of the filter caracteristics is apt to differ from designed value due to the inaccuracy of the resistances or the capacitances of the resistive elements and capacitive elements, e.g., the resistors R42, R44 and the capacitor 22. As a result, the time constant must be adjusted by the control of the current I28 and/or I40 of the current sources 28, 40. Further, the time constant is apt to vary due to the unstableness of the resistances or the capacitances of the resistive elements and capacitive elements. Therefore, such an adjustment is required to be made as the occasion may demand. However, when the filter circuit is fabricated in an IC configuration, the need for such an adjustment of the time constant is undesirable. This is because the IC requires an additional pin for receiving the control voltage Vc for this adjustment. In the prior art, there is no suitable means to automatically carry out this adjustment. In the filter circuit, as shown in FIG. 4, a means to correct by utilizing the equivalent resistance obtained by switching the capacitance C22 of the capacitor 22 is present. However, this circuit is unfavorable in terms of noise caused by the switching, and it cannot be used in an analog IC.